This invention relates generally to integrated circuit design and more particularly to automated integrated circuit design by behavioral synthesis.
Over the past several decades, integrated circuits (ICs) have become an integral part of many devices and machines. Custom or semi-custom ICs are often favored over off-the-shelf components for such devices and machines and are often called "Application Specific Integrated Circuits" or "ASICs." To facilitate ASIC design and fabrication under application specific performance requirements or constraints, automated design and manufacturing systems for ASICs have been developed.
A "behavioral synthesis system" is a computer aided design (CAD) system. With such a system, the ASIC inputs, outputs and other parameters are expressed in a hardware description language (HDL) and input into a computer. Behavioral synthesis software then designs a circuit meeting these parameters.
Typically, behavioral synthesis IC design and manufacturing processes begin by describing certain performance or structural constraints in an HDL such as VHDL or VERILOG. Both these HDLs are available in several commercial forms. The HDL description can be processed or "synthesized" to form a "net" or "netlist" specifying components and their interconnections meeting circuit parameters.
It is always desirable to test the integrated circuit after construction. RAMs, ROMs, and multipliers are common test targets, but they may be deeply embedded within the IC logic. Multiplexer or "functional block" isolation is one approach to testing these subcircuits. In this technique, multiplexers synthesize paths from IC input/output (I/O) pads to the targeted subcircuit. Externally generated test enable signals switch the multiplexers into test mode. Functional block isolation suffers the disadvantages of multiplexer delays, routing congestion, and the need for externally generated test vectors or signals. Also, for a limited number of I/O pads, designing a multiplexer configuration to test all the targeted embedded subcircuits may be difficult.
Alternatively, built-in self-test (BIST) circuitry may be fabricated on the integrated circuit itself. BIST logic generates input test patterns for the RAMs, ROMs, or multipliers. The test output data from these subcircuits can either be compared with the input from the BIST directly or compacted. The comparison result is stored in a register and then shifted out of the IC to an external measurement device. In this way, the external measurement device only detects whether a logic fault was found and does not perform signal comparisons.
To implement the BIST circuitry on the IC via behavioral synthesis, it must be described in the netlist once the RAMs, ROMs, and multipliers have been specified. Modifying the netlist directly after the subcircuits have been described is a very difficult and time-consuming process since the BIST must be described at the gate level. Therefore, given the subcircuit specifications, describing the BIST circuitry in an HDL before synthesis of the netlist would be advantageous.